1. Field of the Invention
The present invention relates to a waveform formation device, and more particularly, it relates to a waveform formation device incorporated into an IC test device or the like for testing an integrated circuit for electrical characteristic, so as to form various square waveform signals.
2. Background Art
FIG. 4 is a schematic view showing a conventional waveform formation device incorporated into an LSI test device.
As shown in FIG. 4, the waveform formation device is provided with a controller 1 for controlling the entire device. A condition memory 2 is connected to the controller 1. The condition memory 2 stores various condition data required for determining test conditions, such as frequency specifying data, start address data, end adress data and switch data.
The waveform formation device is also provided with an oscillator 3 for generating a reference clock pulse 3a. A frequency divider 4 is connected to the oscillator 3. The frequency divider 4 latches frequency specifying data 1a. read from the condition memory 2 by the controller 1 and divides the clock pulse 3a outputted by the oscillator 3 to produce a period signal 4a of a frequency corresponding to the frequency specifying data 1a.
An address controller 5 generates an address signal 5a in synchronization with the period signal 4a applied by the frequency divider 4 to control a data reading operation of a pattern memory 8 discussed later. In this case, a start address in the data reading operation is determined based upon start address data 1b received from the condition memory 2 by the controller 1, while an end address is determined based upon end address data 1b applied similarly from the condition memory 2.
Thus, control means 6 is composed of the controller 1, the condition memory 2, the oscillator 3, the frequency divider 4 and the address controller 5, and the control means 6 controls waveform formation means 7 to a plurality of channels, respectively.
Each of the waveform formation means 7 to the channels includes a pattern memory 8, a plurality of timing generators 9A, 9B, . . . , 9N, a formatter circuit 10 and a driver circuit 11.
The pattern memory 8 stores pattern data "1" or "0" corresponding to each address, and the formatter circuit 10 sequentially reads pattern data 8a of a corresponding address in accordance with the address signal 5a received from the address controller 5.
The timing generators 9A to 9N latch their respective timing data 1c received from the condition memory 2 through the controller 1 and generate timing signals 9Aa to 9Na at specified timings corresponding to the respective timing data 1c in synchronization with the period signal 4a of the frequency divider 4, respectively, so as to apply them to the formatter circuit 10. In this case, the timing generators 9A to 9N measure time, using the reference clock pulse 3a received from the oscillator 3, to determine respective timings.
The formatter circuit 10 produces a desired square waveform signal 10a based upon the pattern data 8a received from the pattern memory 8, the timing signals 9Aa to 9Na received from the timing generators 9A to 9N and switch data 1d received from the condition memory 2 through the controller 1 (this will be explained in detail hereinafter).
The level of the square waveform signal 10a is converted by the driver circuit 11, and thereafter it is applied to a device to be tested as a test signal 11a.
The operation of the waveform formation device incorporated into the LSI test device will now be described with reference to a timing chart shown in FIG. 5.
When the controller 1 receives test starting instructions from outside, various condition data required for determining conditions of the test, namely, the frequency specifying data 1a, the start address data 1b, the end address data 1b, the timing data 1c and the switch data 1d, are first read from the condition memory 2 and then transferred to the frequency divider 4, the address controller 5, the timing generators 9A to 9N and the formatter circuit 10, respectively.
Then, the oscillator 3 starts to apply the clock pulse 3a to the frequency divider 4. This causes the frequency divider 4 to start to divide the clock pulse 3a based upon the frequency specifying data 1a received from the condition memory 2, and thus the period signal 4a shown by (A) of FIG. 5 is produced. The period signal 4a is applied to the address controller 5 and the timing generators 9A to 9N to the channels.
When the address controller 5 receives the period signal 4a, the address signal 5a shown by (B) of FIG. 5 is produced, and the pattern memory 8 starts reading data with regard to each of the channels.
For instance, paying attention to the waveform formation means 7 to a first channel, as shown by (C) of FIG. 5, the pattern data 8a of "1" or "0" stored in a corresponding address is sequentially read from the pattern memory 8 based upon the address signal 5a and applied to the formatter circuit 10. An example in FIG. 5 presents a case in which the start address data 1b set in the address controller 5 is "0", where the pattern data 8a is sequentially read in order of address with a leading address of address "0". The reading operation is executed until it goes to an address corresponding to the end address data 1b.
Meanwhile, when the period signal 4a is applied to the timing generators 9A to 9N to the first channel, as shown by (D) of FIG. 5, in synchronization with the period signal 4a, the timing signal 9Aa to 9Na are produced at specified timings corresponding to the timing data 1c set in the timing generators 9A to 9N in advance, respectively, and then applied to the formatter circuit 10.
In the formatter circuit 10, the square waveform signal 10a is produced based upon the pattern data 8a received from the pattern memory 8, the timing signals 9Aa to 9Na received from the timing generators 9A to 9N and the switch data 1d received from the condition memory 2 in the manner discussed below. Based upon the switch data 1d, a timing signal for determining a timing of the rise and a timing signal for determining a timing of the fall are selected from the timing signals 9Aa to 9Na respectively. For example, with an example of FIG. 5, the timing signal 9Aa is selected as the timing signal for determining a timing of the rise, while the timing signal 9Na is selected as the timing signal for determining a timing of the fall. As shown by (C) of FIG. 5, when "1" is applied as the pattern data 8a, as shown by (E) of FIG. 5, the square waveform signal 10a is produced which rises at the timing of the timing siganl 9Aa and falls at the timing of the timing signal 9Na. On the other hand, when "0" is applied as the pattern data 8a, the square waveform signal 10a is kept at a low level. In this way, the square waveform signal 10a having specified square waveforms is produced.
The level of the square waveform signal 10a is converted by the driver circuit 11 and it is applied to the device to be tested as the test signal 11a.
The above-mentioned operation has been discussed in conjuction with the waveform formation means 7 to the first channel, but a similar operation is performed in the waveform formation means 7 to other channels; that is, the test siganls 11a having various square waveforms are produced based upon the pattern data 8a stored in the pattern memory 8 to the channels and the condition data 1c, 1d to the channels received from the condition memory 2, and then applied to the device to be tested.
In the conventional waveform formation device, for producing the test signals 11a, to the channels, it is required to set data while considering the mutual relations between the pattern data 8a and the condition data, such as the timing data 1c and the switch data 1d; there arises the problem that complicated data setting work is necessary. Such data setting work must be done whenever the test condition is changed, and it is very laborious work.
With the conventional waveform formation device, the timings of the rise and the fall of the square waveform signal 10a is uniformly determined based upon the switch data 1d and the timing data 1c, and during the test operation, the timing can not be freely changed. Hence, with the LSI test device provided with such a waveform formation device, a logical test in which simply high and low levels are required as the test signals 11a can be done without difficulty, but there arises the problem that an AC characteristic test in which the rise and fall timings of the test signal 11a must be varied as time elapses can not be done.